PXR40RM Datasheet, PDF (776/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
MODE[6] = 1
Phase A (from UC[n])
Phase B (from UC[n – 1])
EMIOS_CCNTR[n]
inc/dec
+1 +1 +1 +1 +1 +1 +1 +1 –1 –1 –1 –1 –1 –1 –1 +1 +1 +1 +1 +1 +1 +1 +1 –1 –1 –1 –1 –1 –1 –1 +1 +1 +1 +1 +1 +1 +1
A1 Write
EMIOS_CCNTR[n]
(Value 1)
A1 Match
A1 Match
A1 Write
(Value 2)
A1 Match
A1 Match
A1 Match
Value 2
Value 1
0x000000
FLAG Pin/Register
Note: EMIOS_CADR[n] = A1
Figure 23-30. QDEC Example with Phase_A & Phase_B Encoder
Time
23.4.1.1.10 Windowed Programmable Time Accumulation (WPTA) Mode
The WPTA mode (MODE = 000_1110) accumulates the sum of the total high time or low time of an input
signal over a programmable interval (time window).
The UCPRE[1:0] prescaler bits in the EMIOS_CCR[n] register define the increment rate of the internal
counter.
Register A1 holds the start time and register B1 holds the stop time of the programmable time interval.
When a match occurs between register A (EMIOS_CADR) and the selected timebase, the internal counter
is cleared and it is ready to start counting. The internal counter is used as a time accumulator, i.e., it counts
up when the input signal has the same polarity of the EDPOL bit in the EMIOS_CCR[n] register and does
not count otherwise. When a match occurs in comparator B, the internal counter is disabled regardless of
the input signal polarity and the FLAG bit is set. At the same time, the contents of the EMIOS_CCNTR[n]
register is transferred to register A2. Reading registers EMIOS_CCNTR[n] or A2 returns the high or low
time of the input signal.
Note that EMIOS_CCNTR[n] is stable only outside the time window defined from A1 to B1 matches.
Otherwise, its contents reflect a count in progress and not the final value. Alternatively to
EMIOS_CCNTR[n], register A2 returns the latest available measurement. Since this register is updated
only at comparator B matches, it always contains stable and up-to-date data. In this mode, this register is
accessible through the alternate register address EMIOS_ALTA[n].
Figure 23-31 shows how the unified channel can be used to accumulate high time.
23-36
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor