PXR40RM Datasheet, PDF (930/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Table 26-2. Glossary (continued)
Term
Set
Clear
Asserted
Definition
To set a bit or bits means to establish logic level one on the bit or bits.
To clear a bit or bits means to establish logic level zero on the bit or bits.
A signal that is asserted is in its active state. An active low signal changes from logic level one to logic level
zero when asserted, and an active high signal changes from logic level zero to logic level one.
Preamble
Bit time
frame
LIN byte field
SCI frame
LIN frame
LIN TX frame
LIN RX frame
The term preamble describes an idle character which is transmitted by the eSCI module.
Duration of a single bit in a transmitted byte field or character, equivalent to the duration of one transmitter
clock cycle defined in Section 26.4.3.2, Transmitter Clock
Entity that consists of the start bit followed by payload bits followed by one ore more stop bits
Special instance of a frame
Special instance of a frame
Sequence of break character followed by LIN byte fields
A LIN frame with the frame header, data byte fields, and checksum field transmitted by the eSCI module
A LIN frame with the header field transmitted by the eSCI module and the data byte fields and checksum field
received by the eSCI module
26.1.4 Overview
The eSCI block allows asynchronous serial communications with peripheral devices and other CPUs. It
includes special support to interface to LIN slave devices.
26-2
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor