PXR40RM Datasheet, PDF (1215/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
29.2.10.3 ETPUCxHSRR - eTPU Channel x Host Service Request Register
ETPUCxHSRR is used by the Host to issue service requests to the channel.
Channel_Register_Base + 0x8
0
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W
RESET: 0
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HSR
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RESET: 0
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= Unimplemented or Reserved
Figure 29-25. ETPUCxHSRR Register
HSR[0:2] — Host Service Request
This field is used by the Host CPU to request service to the channel (see Section 29.3.2.5, Host Service
Requests)
HSR = 000: no Host Service Request pending
HSR > 000: function-dependent Host Service Request pending.
HSR value turns to 000 automatically at the end of microengine service for that channel, but only if the
thread started due to an HSR. Host should write HSR>0 only when HSR=0. Writing HSR=000 withdraws
a pending request if scheduler did not begin to resolve the Entry Point yet, but it does not abort the service
thread from that point on. For more details, see the eTPU Reference Manual and Section 29.3.2.5, Host
Service Requests.
29.3 Functional Description
29.3.1 Watchdog
Each engine has a watchdog mechanism to prevent a thread or a sequence of threads from running too long,
impacting the latency of the other channel services. The watchdog is configured through the register
ETPUWDTR (see Section 29.2.7.1, ETPUWDTR - eTPU Watchdog Timer Register). When the watchdog
is enabled, an internal counter increments on each microcycle when a thread is executing. If the count is
greater than the value specified in the ETPUWDTR field WDCNT and a thread is still executing, the
watchdog:
1. Forces an END of the thread
2. Issues a Global Exception and sets the ETPUMCR bit WDTO (see Section 29.2.5.1, ETPUMCR -
eTPU Module Configuration Register).
The watchdog can be configured in one of the following modes, defining how the internal watchdog count
is reset:
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-47