PXR40RM Datasheet, PDF (488/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Error Correction Status Module (ECSM)
This register is read-only; any attempted write is ignored. See Figure 17-5 and Table 17-7 for the flash
ECC address register definition.
Offset: ECSM_BASE_ADDR + 0x0050
Access: User read-only
0
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FEAR
W
Reset U¹
U
U
U
U
U
U
U
U
UU U
U
U
U
U
16
R
W
Reset U
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FEAR
U
U
U
U
U
U
U
U
UU U
U
U
U
U
1 _{U = undefined at reset}
Figure 17-5. Flash ECC Address (ECSM_FEAR) Register
Table 17-7. ECSM_FEAR Field Descriptions
Field
Description
0–15 Flash ECC Address Register. Contains the faulting access address of the last, properly enabled flash ECC event.
FEAR
17.2.2.9 Flash ECC Master Number Register (ECSM_FEMR)
The ECSM_FEMR is an 8-bit register for capturing the XBAR bus master number of the last,
properly-enabled ECC event in the flash memory. Depending on the state of the ECC Configuration
Register, an ECC event in the flash causes the address, attributes and data associated with the access to be
loaded into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers and also the
appropriate flag (FNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See Figure 17-6 and Table 17-8 for the flash
ECC master number register definition.
Offset: ECSM_BASE_ADDR + 0x0056
Access: User read-only
0
1
2
3
4
5
6
7
R
0
0
0
0
FEMR
W
Reset
0
0
0
0
U¹
U
U
U
Figure 17-6. Flash ECC Master Number (ECSM_FEMR) Register
1 _{U = undefined at reset}
Table 17-8. ECSM_FEMR Field Descriptions
Field
Description
0–7 Flash CC Master Number Register. Contains the XBAR bus master number of the faulting access of the last,
FEMR properly enabled flash ECC event.
17-10
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor