PXR40RM Datasheet, PDF (317/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Interrupts and Interrupt Controller (INTC)
Table 10-8. Interrupt Request Sources (continued)
Hardware
Vector Mode
Offset
0x0530
0x0540
0x0550
0x0560
0x0570
0x0580
0x0590
0x05A0
0x05B0
0x05C0
0x05D0
0x05E0
0x05F0
0x0600
0x0610
0x0620
0x0630
0x0640
0x0650
0x0660
0x0670
0x0680
0x0690
0x06A0
0x06B0
0x06C0
0x06D0
0x06E0
Vector
Number ¹
Source²
83 ETPU_CISR_A[CIS15]
84 ETPU_CISR_A[CIS16]
85 ETPU_CISR_A[CIS17]
86 ETPU_CISR_A[CIS18]
87 ETPU_CISR_A[CIS19]
88 ETPU_CISR_A[CIS20]
89 ETPU_CISR_A[CIS21]
90 ETPU_CISR_A[CIS22]
91 ETPU_CISR_A[CIS23]
92 ETPU_CISR_A[CIS24]
93 ETPU_CISR_A[CIS25]
94 ETPU_CISR_A[CIS26]
95 ETPU_CISR_A[CIS27]
96 ETPU_CISR_A[CIS28]
97 ETPU_CISR_A[CIS29]
98 ETPU_CISR_A[CIS30]
99 ETPU_CISR_A[CIS31]
100
EQADC_FISRx[TORF]
EQADC_FISRx[RFOF]
EQADC_FISRx[CFUF]
101 EQADC_FISR0[NCF]
102 EQADC_FISR0[PF]
103 EQADC_FISR0[EOQF]
104 EQADC_FISR0[CFFF]
105 EQADC_FISR0[RFDF]
106 EQADC_FISR1[NCF]
107 EQADC_FISR1[PF]
108 EQADC_FISR1[EOQF]
109 EQADC_FISR1[CFFF]
110 EQADC_FISR1[RFDF]
Description
eTPU engine A channel 15 interrupt status
eTPU engine A channel 16 interrupt status
eTPU engine A channel 17 interrupt status
eTPU engine A channel 18 interrupt status
eTPU engine A channel 19 interrupt status
eTPU engine A channel 20 interrupt status
eTPU engine A channel 21 interrupt status
eTPU engine A channel 22 interrupt status
eTPU engine A channel 23 interrupt status
eTPU engine A channel 24 interrupt status
eTPU engine A channel 25 interrupt status
eTPU engine A channel 26 interrupt status
eTPU engine A channel 27 interrupt status
eTPU engine A channel 28 interrupt status
eTPU engine A channel 29 interrupt status
eTPU engine A channel 30 interrupt status
eTPU engine A channel 31 interrupt status
eQADC A
eQADC A combined overrun interrupt request s from all of the
FIFOs:
• Trigger overrun,
• Receive FIFO overflow,
• Command FIFO underflow
eQADC A command FIFO 0 non-coherency flag
eQADC A command FIFO 0 pause flag
eQADC A command FIFO 0 command queue end-of-queue flag
eQADC A command FIFO 0 fill flag
eQADC A receive FIFO 0 drain flag
eQADC A command FIFO 1 non-coherency flag
eQADC A command FIFO 1 pause flag
eQADC A command FIFO 1 command queue end-of-queue flag
eQADC A command FIFO 1 fill flag
eQADC A receive FIFO 1 drain flag
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
10-17