PXR40RM Datasheet, PDF (261/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
SIU_BASE + 0xD00, SIU_BASE + 0xD08, SIU_BASE + 0xD10, SIU_BASE + 0xD18
R
W
RESET:
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
W
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-31. Masked Serial GPO Register for DSPI - DSPI_A/B/C/D GPO Mask Output High Register
(SIU_DSPIAH/SIU_DSPIBH/SIU_DSPICH/SIU_DSPIDH)
SIU_BASE + 0xD04, SIU_BASE + 0xD0C, SIU_BASE + 0xD14, SIU_BASE + 0xD1C
R
W
RESET:
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
W
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-32. Masked Serial GPO Register for DSPI - DSPI_A/B/C/D GPO Mask Output Low Register
(SIU_DSPIAL/SIU_DSPIBL/SIU_DSPICL/SIU_DSPIDL)
Table 7-53. SIU_DSPIAL/SIU_DSPIBL/SIU_DSPICL/SIU_DSPIDL Field Descriptions
Field
0–15
MASKx
16–31
DATAx
Description
Pin Data Out. Controls the write access to the corresponding GPO for DSPI. These bits are write-only and
read as 0.
0 Previous value defined by GPDO is maintained.
1 Corresponding GPO is written with value defined by DATA field.
Note: The MASK bits have to be written at the same time (same access cycle) as the DATA bits, for the mask
to work (the MASK information is not stored).
Pin Data Out. Stores the data to be driven out on the external GPIO pin controlled by this register.
0 Logic low value is driven on the pad interface data out signal for the corresponding GPO for DSPI when
this output is selected in the DSPI serialization module.
1 Logic high value is driven on the pad interface data out signal for the corresponding GPO for DSPI when
this output is selected in the DSPI serialization module.
7.3.1.33.2 Serialized Output Signal Selection Registers for DSPI_A
The following three registers are used by DSPI_A to select the sources of the serialized output when
running in DSI or CSI configuration.
Each register bit enables a path from the eTPU_B channel, eMIOS channel and data register bit
SIU_DSPIAH/SIU_DSPIAL to the equivalent bit position in the DSPI_A serialized output frame. The
user must ensure that bit selections from each of these registers do not overlap. Multiple sources are
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-79