PXR40RM Datasheet, PDF (263/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
SIU_BASE + 0xD48
R
W
RESET:
0
DSPI
AH
0
0
1
DSPI
AH
1
0
2
DSPI
AH
2
0
3
DSPI
AH
3
0
4
DSPI
AH
4
0
5
DSPI
AH
5
0
6
DSPI
AH
6
0
7
DSPI
AH
7
0
8
DSPI
AH
8
0
9
DSPI
AH
9
0
10
DSPI
AH
10
0
11
DSPI
AH
11
0
12
DSPI
AH
12
0
13
DSPI
AH
13
0
14
DSPI
AH
14
0
15
DSPI
AH
15
0
R
W
RESET:
16
DSPI
AL
16
0
17
DSPI
AL
17
0
18
DSPI
AL
18
0
19
DSPI
AL
19
0
20
DSPI
AL
20
0
21
DSPI
AL
21
0
22
DSPI
AL
22
0
23
DSPI
AL
23
0
24
DSPI
AL
24
0
25
DSPI
AL
25
0
26
DSPI
AL
26
0
27
DSPI
AL
27
0
28
DSPI
AL
28
0
29
DSPI
AL
29
0
30
DSPI
AL
30
0
31
DSPI
AL
31
0
Figure 7-35. SIU_DSPIAH/L Select Register for DSPI_A (SIU_DSPIAHLA)
Table 7-56. SIU_DSPIAHLA Field Descriptions
Field
Description
0–31
DSPI_A Data Register bit
DSPIAH/Lx 0 The corresponding serial GPO A output (from the SIU_DSPIAH/L register) is disabled
1 The corresponding serial GPO A output (from the SIU_DSPIAH/L register) is enabled
7.3.1.33.3 Serialized Output Signal Selection Registers for DSPI_B
The following three registers are used by DSPI_B to select the sources of the serialized output when
running in DSI or CSI configuration.
Each register bit enables a path from the eTPU_A channel, eMIOS channel and data register bit
SIU_DSPIBH/SIU_DSPIBL to the equivalent bit position in the DSPI_B serialized output frame. The user
must ensure that bit selections from each of these registers do not overlap. Multiple sources are logically
ORed, which provides the potential for combining outputs from multiple timer channels and data registers
to produce more complex bit behavior.
SIU_BASE + 0xD50
R
W
RESET:
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA
23 22 21 20 19 18 17 16 29 28 27 26 25 24 31 30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA
12 13 14 15 0
1
2
3
4
5
6
7
8
9 10 11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-36. eTPU_A Select Register for DSPI_B (SIU_ETPUAB)
Table 7-57. SIU_ETPUAB Field Descriptions
Field
Description
0–31
ETPUA channel select
ETPUAx 0 This bit in the DSPI_B serialized output frame will not use the respective ETPUA channel
1 This bit in the DSPI_B serialized output frame will use the respective ETPUA channel
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-81