PXR40RM Datasheet, PDF (779/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
MODE[4] = 1
EMIOS_CCNTR[n]
0xFFFFFF
0x000303
0x000200
Write
to A2
A1 Match
B1 Match
(= 0)
Write
to A2
A1 Match
B1 Match
(= 0)
0x000000
A1 Value¹ 0xxxxxxx
FLAG Pin/Register
0x000303
0x000303
0x000200 0x000200
Notes: 1. EMIOS_CADR[n] = A1
A2 = A1 according to OU[n] bit
Figure 23-33. MC Up/Down Mode Example
0x000200
Time
23.4.1.1.12 Modulus Counter Buffered (MCB) Mode
The MCB mode provides a time base that can be shared with other channels through the internal counter
buses. Register A1 is double-buffered, thus allowing smooth transitions between cycles when changing
the A2 register value on the fly. Register A1 is updated at the cycle boundary, which is defined as when
the internal counter reaches the value 0x00_0001.
The internal counter values operate within a range from 0x00_0001 up to the value of register A1 in MCB
mode. When entering MCB mode (coming out of GPIO mode), the internal counter value must be within
that range. Otherwise, the first A match will not occur, causing the channel internal counter to wrap at the
maximum counter value of 0xFF_FFFF. After the counter wrap occurs, it returns to 0x00_0001 and
resumes normal MCB mode operation. To avoid this counter wrap condition, make sure the internal
counter value is within the 0x00_0001 to A1 register value range when entering the MCB mode.
MODE[6] bit selects the internal clock source if set to 0, or external if set to 1. When the external clock is
selected, the input channel pin is used as the channel clock source. The active edge of this clock is defined
by the EDPOL and EDSEL bits in the EMIOS_CCR[n] channel register.
When entering MCB mode, if the up counter is selected by MODE[4] = 0, the internal counter starts
counting up from its current value until the A1 match occurs. On the next system clock cycle after the A1
match, the internal counter is set to 0x00_0001 and the FLAG bit is set to '1'.
If the up/down counter is selected by setting MODE[4] = 1, the counter changes direction at the A1 match
and counts down until it reaches 0x00_0001. After it reaches 0x00_0001, it counts up again. Register B1
is set to 0x00_0001 on entering MCB mode cannot be changed while this mode is selected. B1 is used to
generate a match to set the internal counter in up-count direction if up/down mode is selected.
The MCB mode counts between 0x00_0001 and the value in the A1 register. Only values greater than
0x00_0001 are allowed to be written to the A1 register. Loading values other than those leads to
unpredictable results. The counter cycle period is equal to A1 value in up counter mode. If in up/down
counter mode the period is defined by the expression: (2 × A1) – 2.
Figure 23-34 shows the counter cycle for several A1 values. Register A1 is loaded with the value in A2 at
the cycle boundary. Any value written to the A2 register within cycle (n) is updated to A1 at the next cycle
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-39