PXR40RM Datasheet, PDF (1253/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
Finding the WCL for PWM on Channel 0
The following shows how to find the WCL for PWM on channel 0.
1. Find the worst-case service time for each active channel.
a. Longest thread of PWM is 24 CPU clocks with four RAM accesses.
24 + ((4 RAM accesses+1) * 0.09 * 2 CPU clock waits) = 24.9 CPU clocks, rounded up to 25
CPU clocks (since there are no partial clock periods)
Channel 0 worst-case service time = 25 CPU clocks.
b. Longest thread of PPWA in mode 0 is 44 CPU clocks with nine RAM accesses.
44 + ((9 RAM accesses+1) * 0.09 * 2 CPU clock waits) = 45.8 CPU clocks, rounded up to 46
CPU clocks
Channel 1 worst-case service time = 46 CPU clocks.
c. Longest thread of DIO is ten CPU clocks with four RAM accesses.
10 + ((4 RAM accesses+1) * 0.09 * 2 CPU clock waits) = 10.9 CPU clocks, rounded up to 11
CPU clocks
Channel 2 worst-case service time = 11 CPU clocks.
2. Assume channel 0 has just been serviced and that channels 1 and 2 are continuously requesting
service. Using the H-M-H-L-H-M-H time-slot sequence, map the channels that are granted for
each time slot. See Figure 29-39.
WORST CASE LATENCY
CHANNEL 0
HM H LH MH H
= 10-CYCLE TIME SLOT TRANSITION
= 4-CYCLE NOP INSTRUCTION
CHANNEL 0
SERVICED
CHANNEL 0
SERVICED
CHANNEL 1
SERVICED
Figure 29-39. Next Servicing for Channel 0
TPU CH0 WCL TIM
Channel 1 will be serviced in the middle-priority time slot before channel 0 is serviced again.
3. Add time for the six-clock CPU time-slot transitions. See Figure 29-39 and Table 29-23.
A four-clock NOP occurs after each channel is serviced since there is one channel in each priority
level, i.e., a new cycle for a priority level is started after each channel is serviced. Time-slot
transitions occur after each time slot.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-85