PXR40RM Datasheet, PDF (1170/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
Instructions executed by the eTPU are connected directly to the eTPU timing hardware and allow
parallelism of hardware related actions.
29.1.1 Overview
Figure 29-1 shows a top-level eTPU A/B Module block diagram. It displays a dual eTPU Engine
configuration. The eTPU C Module contains a single eTPU Engine configuration.
HOST CPU
SCM
SHARED CODE MEMORY
STAC
signals
Debug If
REGISTERS
eTPU Engine A
SHARED
BIU
SHARED
P.RAM
REGISTERS
eTPU Engine B
STAC
signals
Debug If
PINS
PINS
Figure 29-1. eTPU A/B Module Block Diagram
eTPU Engine is responsible for processing input pin transitions and output pin waveform generation
based on the Time Bases. Each eTPU Engine has its own microprocessor and dedicated hardware for
processing signals on I/O pins and can also interface with external time bases through the STAC bus.
Both eTPU Engine CPUs, hereafter called microengines, fetch microinstructions from a Shared Code
Memory - SCM.
29-2
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor