PXR40RM Datasheet, PDF (350/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

General-Purpose Static RAM (SRAM)
Table 11-3. Number of Wait States Required for SRAM Operations (continued)
Current Operation
8-, 16-, or 32-bit write
Previous Operation
Idle
Read
Pipelined 8-, 16-, or 32-bit write
64-bit write
8-, 16-, or 32-bit write
Pipelined 8-, 16-, or 32-bit write
64-bit write
64-bit burst write
8-, 16-, or 32-bit write
Idle
64-bit write
Read
Idle
64-bit write
Read
Number of Wait States Required
1
2
0
(write to the same address)
0
0
0,0,0,0
11.6.2 Reset Effects on SRAM Accesses
If a reset event asserts during a read or write operation to SRAM, the completion of that access depends
on the cycle at which the reset occurs. Data read from or written to SRAM before the reset event occurred
is retained, and no other address locations are accessed or changed.
If the system SRAM is cached, cache lines can retain indeterminate data that is not written to memory
unless the region is set for write-through mode.
NOTE
Standby memory can contain the previous data values if a reset occurs while
cache is running in copy back mode.
11.7 Initialization and Application Information
To use the SRAM, the ECC must check all bits that require initialization after power on. Use a 64-bit
cache-inhibited write to each SRAM location to initialize the SRAM array as part of the application
initialization code. All writes must specify an even number of registers performed on 64-bit word-aligned
boundaries. If the write is not the entire 64-bits (8-, 16-, or 32-bits), a read / modify / write operation is
generated that checks the ECC value upon the read. See Section 11.6, SRAM ECC Mechanism.
NOTE
You must initialize SRAM, even if the application does not use ECC
reporting.
11-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor