PXR40RM Datasheet, PDF (309/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Interrupts and Interrupt Controller (INTC)
10.3.1 Register Descriptions
With the exception of the INTC_SSCIn and INTC_PSRn registers, all of the registers are 32-bits wide.
Any combination of accessing the 4 bytes of a register with a single access is supported, provided that the
access does not cross a register boundary. These supported accesses include types and sizes of 8 bits,
aligned 16 bits, and aligned 32 bits.
Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or
32-bit access, provided that the access does not cross a 32-bit boundary.
In software vector mode, the side effects of a read of the INTC interrupt acknowledge register
(INTC_IACKR) are the same regardless of the size of the read. In either software or hardware vector
mode, the size of a write to the INTC end-of-interrupt register (INTC_EOIR) does not affect the operation
of the write.
10.3.1.1 INTC Module Configuration Register (INTC_MCR)
The INTC_MCR is used to configure options of the INTC.
Address: Base + 0x0000 (INTC_MCR)
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000
VTES
HVEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 10-7. INTC Module Configuration Register (INTC_MCR)
Table 10-3. INTC_MCR Field Descriptions
Field
Description
0–25 Reserved, must be cleared.
26
VTES
Vector table entry size. Controls the number of ‘0’s to the right of INTVEC in Section 10.3.1.3, INTC Interrupt
Acknowledge Register (INTC_IACKR). If the contents of INTC_IACKR are used as an address of an entry in a vector
table as in software vector mode, then the number of right-most ‘0’s determines the size of each vector table entry.
VTES impacts software vector mode operation but also affects the INTC_IACKR[INTVEC] position in both hardware
vector mode and software vector mode.
0 4 bytes
1 8 bytes
27–30 Reserved, must be cleared.
31
HVEN
Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector mode. Refer to
Section 10.1.4, Modes of Operation, for the details of the handshaking with the processor in each mode.
0 Software vector mode
1 Hardware vector mode
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
10-9