PXR40RM Datasheet, PDF (788/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
EDPOL = 0
Prescaler = 1
EMIOS_CCNTR[n]
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Output Pin
A1 Value
A2 Value
B1 Value
100%
Time
0%
0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002
0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001
0x000008
Figure 23-44. OPWFMB Mode from 100% to 0% Duty Cycle
0x000001
0x000000
0x000000
A 0% duty cycle signal is generated if A1 = 0x00_0000 as shown in cycle 9 in Figure 23-44. In this case,
the B1 = 0x00_0008 match from cycle 8 occurs at the same time as the A1 = 0x00_0000 match from cycle
9. Refer to Figure 23-41 for a description of the A1 and B1 match generation. In this case, the A1 match
has precedence over the B1 match and the output signal transitions to EDPOL.
23.4.1.1.15 Center Aligned Output Pulse Width Modulation with Dead Time (OPWMC)
Mode
The OPWMC mode generates a center aligned PWM with dead time insertion in the leading
(MODE = 001_11b1) or trailing edge (MODE = 001_11b0).
The selected counter bus must be running an up/down time base, as shown in Figure 23-33. BSL[1:0] bits
select the time base. Register A1 contains the ideal duty cycle for the PWM signal and is compared with
the selected time base. Register B1 contains the dead time value and is compared with the internal counter.
For a leading-edge dead time insertion, the output PWM duty cycle is equal to the difference between
register A1 and register B1, and for a trailing edge dead time insertion, the output PWM duty cycle is equal
to the sum of register A1 and register B1. Mode[6] bit selects between trailing and leading dead time
insertion.
NOTE
The internal counter may be running in the internal prescaler ratio, while
the selected time base may be running in a different prescaler ratio. The
output signal may produce an unexpected output if the dead time interval is
greater than the duty cycle of the PWM signal.
When OPWMC mode is entered, coming out from GPIO mode, the output flip-flop is set to the
complement of the EDPOL bit in the EMIOS_CCR[n] register.
When operating with leading edge dead time insertion, the first match between A1 and the selected time
base clears the internal counter and switches the selected time base to the internal counter. When a match
occurs between register B1 and the selected time base, the output flip-flop is set to the value of the EDPOL
bit and the time base is switched to the selected counter bus. In the next match between register A1 and
the selected time base, the output flip-flop is set to the complement of the EDPOL bit. This sequence
repeats continuously.
23-48
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor