PXR40RM Datasheet, PDF (669/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
System Memory
FIFO Message Buffer Data Area
Message Buffer Header Fields
Receive FIFO B
Message Buffer Header Fields
Receive FIFO A
RFSYMBADR[SMBA]
Frame Header
Frame Header
Frame Header
Frame Header
Data Field Offset
Slot Status
Data Field Offset
Data Field Offset
Slot Status
Slot Status
Data Field Offset
Slot Status
Sync Frame Table Area
Message Buffer Data Area
Message Buffer Header Fields
Individual Message Buffers
Receive Shadow Buffers
Frame Header
Frame Header
Frame Header
Data Field Offset
Slot Status
Data Field Offset
Slot Status
Data Field Offset
Slot Status
SYMBADR[SMBA]
10 bytes
Figure 22-108. Example of FlexRay Memory Layout (MCR[FAM] = 1)
22.6.4.3 Message Buffer Header Area (MCR[FAM] = 0)
The message buffer header area contains all message buffer header fields of the physical message buffers
for all message buffer types. The following rules apply to the message buffer header fields for the three
type of message buffers.
1. The start byte address SADR_MBHF of each message buffer header field for individual message
buffers and receive shadow buffers must fulfill Equation 22-7.
SADR_MBHF = (i * 10) + SYMBADR[SMBA]; (0 <= i < 256)
Eqn. 22-7
2. The start byte address SADR_MBHF of each message buffer header field for the FIFO must fulfill
Equation 22-8.
SADR_MBHF = (i * 10) + SYMDARD[SMBA]; (0 <= i < 1024)
Eqn. 22-8
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-85