PXR40RM Datasheet, PDF (271/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
When the counter for an IRQ is not enabled, the state of the IRQ is held in the current and previous state
latches. The IRQ counter operates independently of the IRQ or overrun flag bit. Clearing the IRQ flag or
overrun flag bits does not clear or reload the counter.
Refer to the following sections for more information:
• Section 7.3.1.4, External Interrupt Status Register (SIU_EISR)
• Section 7.3.1.9, IRQ Rising-Edge Event Enable Register (SIU_IREER)
• Section 7.3.1.10, IRQ Falling-Edge Event Enable Register (SIU_IFEER)
• Section 7.3.1.11, IRQ Digital Filter Register (SIU_IDFR)
7.4.3.0.1 External Interrupts
The IRQ signals map to 16 independent interrupt requests output from the SIU. The IRQ flag bit is set
when a rising-edge and/or falling-edge event occurs for the IRQ. An external IRQ signal is asserted when
all of the following occur:
• Enable bit is set in the IRQ rising- and/or falling-edge event registers (SIU_IREER, SIU_IFEER)
• IRQ flag bit is set in the external interrupt status register (SIU_EISR)
• Enable bit is cleared in the DMA/Interrupt request enable register (SIU_DIRER)
• Select bit is cleared in the DMA/Interrupt select register (SIU_DIRSR)
The NMI pin function or platform SWT can generate either an NMI or a critical interrupt. When
WKPCFG_NMI_GPIO213 is enabled as NMI, the pin will override the PCR configuration after reset.
SIU_DIRER selects between critical and non maskable interrupt use, SIU_EISR reports status of NMI and
SIU_IFEER selects edge sensitivity of NMI input
Refer to the following sections for more information:
• Section 7.3.1.5, DMA/Interrupt Request Enable Register (SIU_DIRER)
• Section 7.3.1.6, DMA/Interrupt Request Select Register (SIU_DIRSR)
7.4.3.0.2 DMA Transfers
DMA IRQ signals (IRQ[0] through IRQ[3]) map to four independent DMA transfer or interrupt request
outputs configured in the SIU. A DMA transfer or interrupt request asserts when all of the following occur:
• IRQ flag bit is set in the external interrupt status register (SIU_EISR)
• Enable bit is set in the DMA transfer or interrupt request enable register (SIU_DIRER)
• Select bit is set in the DMA transfer or interrupt request select register (SIU_DIRSR)
The SIU receives a ‘DMA transfer done’ signal for each DMA or interrupt request transmitted.
When the ‘DMA done’ signal asserts, the IRQ flag bit is cleared.
Refer to the following sections for more information:
• Section 7.3.1.5, DMA/Interrupt Request Enable Register (SIU_DIRER)
• Section 7.3.1.6, DMA/Interrupt Request Select Register (SIU_DIRSR)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-89