PXR40RM Datasheet, PDF (1323/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
31.2.1.5 Ready (RDY)
RDY is an output pin that indicates when a device is ready for the next access.
31.2.1.6 JTAG Compliancy (JCOMP)
The JCOMP signal enables or disables the TAP controller. The TAP controller is enabled when JCOMP
asserts, otherwise the TAP controller remains in reset.
31.2.1.7 Test Data Output (TDO)
The TDO pin transmits serial output for instructions and data. TDO is tri-stateable and is actively driven
in the SHIFT-IR and SHIFT-DR controller states. TDO is updated on the falling edge of TCK and sampled
by the development tool on the rising edge of TCK.
31.2.1.8 Test Clock Input (TCK)
The TCK pin is used to synchronize the test logic and control register access through the JTAG port.
31.2.1.9 Test Data Input (TDI)
The TDI pin receives serial test instruction and data. TDI is sampled on the rising edge of TCK.
31.2.1.10 Test Mode Select (TMS)
The TMS pin is used to sequence the IEEE 1149.1-2001 TAP controller state machine. TMS is sampled
on the rising edge of TCK.
31.3 Memory Map
The NDI block contains no memory mapped registers. Nexus registers are accessed by the development
tool via the JTAG port using a register index and a client select value. The client select is controlled by
loading the correct access instruction into the JTAG controller; see Table 31-4. OnCE registers are
accessed by loading the appropriate value in the RS[0:6] field of the OnCE command register (OCMD)
via the JTAG port.
Table 31-2 shows the NDI registers and their Index values.
Table 31-2. Nexus Development Interface (NDI) Registers
Index
Register
NPC Registers
0
Device ID Register (DID)
127 Port Configuration Register (PCR)
e200z7 Control and Status Registers¹
2
e200z7 Development Control1 (NZ7C3_DC1)
3
e200z7 Development Control2 (NZ7C3_DC2)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
31-7