PXR40RM Datasheet, PDF (561/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Field
65
0x8 [1]
DMLOE ¹
66–85
0x8 [2-21]
MLOFF or
NBYTES ¹
86–95 /
0x8 [22:31]
NBYTES ¹
96–127 /
0xC [0:31]
SLAST
128–159 /
0x10 [0:31]
DADDR
160 /
0x14 [0]
CITER.E_LINK
161–166 /
0x14 [1:6]
CITER
or
CITER.LINKCH
Enhanced Direct Memory Access Controller (eDMA)
Table 21-21. TCDn Field Descriptions (continued)
Description
Destination minor loop offset enable
This flag selects whether the minor loop offset is applied to the destination address upon
minor loop completion.
0 The minor loop offset is not applied to the daddr.
1 The minor loop offset is applied to the daddr.
Inner “minor” byte transfer count or Minor loop offset
If both SMLOE and DMLOE are cleared, this field is part of the byte transfer count.
If either SMLOE or DMLOE are set, this field represents a sign-extended offset applied to the
source or destination address to form the next-state value after the minor loop is completed.
Inner “minor” byte transfer count. Number of bytes to be transferred in each service request
of the channel. As a channel is activated, the contents of the appropriate TCD is loaded into
the eDMA engine, and the appropriate reads and writes performed until the complete byte
transfer count has been transferred. This is an indivisible operation and cannot be stalled or
halted. Once the minor count is exhausted, the current values of the SADDR and DADDR are
written back into the local memory, the major iteration count is decremented and restored to
the local memory. If the major iteration count is completed, additional processing is
performed.
Note: The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying
a 4 GB transfer.
Last source address adjustment. Adjustment value added to the source address at the
completion of the outer major iteration count. This value can be applied to “restore” the source
address to the initial value, or adjust the address to reference the next data structure.
Destination address. Memory address pointing to the destination data.
Enable channel-to-channel linking on minor loop completion. As the channel completes the
inner minor loop, this flag enables the linking to another channel, defined by
CITER.LINKCH[0:5]. The link target channel initiates a channel service request via an internal
mechanism that sets the EDMA_x_TCD.START bit of the specified channel. If channel linking
is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the
major loop is exhausted, this link mechanism is suppressed in favor of the MAJOR.E_LINK
channel linking.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
Note: This bit must be equal to the BITER.E_LINK bit. Otherwise, a configuration error is
reported.
Current major iteration count or link channel number.
If channel-to-channel linking is disabled (EDMA_x_TCD.CITER.E_LINK = 0), then
• No channel-to-channel linking (or chaining) is performed after the inner minor loop is
exhausted. TCD bits [161:175] are used to form a 15-bit CITER field.
Otherwise,
• After the minor loop is exhausted, the DMA engine initiates a channel service request at
the channel defined by CITER.LINKCH[0:5] by setting that channel’s
EDMA_x_TCD.START bit.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21-37