PXR40RM Datasheet, PDF (1331/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
• Controls arbitration for ownership of the Nexus auxiliary output port
• Nexus device identification register and messaging
• Generates MCKO enable and frequency division control signals
• Controls sharing of EVTO
• Control of the device-wide debug mode
• Generates asynchronous reset signal for Nexus modules based on JCOMP input, censorship status,
and power-on reset status
• Provides Nexus support for censorship mode
31.6 NPC Memory Map and Register Definition
This section provides a detailed description of the NPC registers accessible to the end user. Individual
bit-level descriptions and reset states of the registers are included.
31.6.1 Memory Map
Table 31-9 shows the NPC registers by index values. The registers are not memory-mapped and can only
be accessed via the TAP. The NPC does not implement the client select control register because the value
does not matter when accessing the registers. The bypass register (see Section 31.6.2.1, Bypass Register)
and instruction register (see Section 31.6.2.2, Instruction Register) have no index values. These registers
are not accessed in the same manner as Nexus client registers.
Table 31-9. NPC Memory Map
Index
0
127
Register
Bits
DID—Device ID register
32
PCR—Port configuration register 32
Access
R
R/W
Reset Value Section/Page
0x0827_401D 31.6.2.4/31-17
0x0000_0000 31.6.2.4/31-17
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
31-15