PXR40RM Datasheet, PDF (228/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
Table 7-26. SIU_DISR Bit Field Descriptions (continued)
Field
Description
26–27
SSSELD
28–29
SCKSELD
30–31
TRIGSELD
DSPI D slave select input select. Specifies the source of the DSPI D slave select
input.
00 PCSB[1]_PCSD[0]_GPIO[106] pin
01 PCSA0 (master)
10 PCSB0 (master)
11 PCSC0 (master)
DSPI D clock input select. Specifies the source of the DSPI D clock input in slave
mode.
00 PCSA[2]_SCKD_GPIO[98] pin
01 Invalid value
10 SCKB (master)
11 SCKC (master)
DSPI D trigger input select. Specifies the source of the DSPI D trigger input for
master or slave mode.
00 Invalid value
01 PCSA4
10 PCSB4
11 PCSC4
7.3.1.18 eQADC Command FIFO Trigger Source Select - IMUX Select Registers
(SIU_ISEL[4-7])
The IMUX select registers (SIU_ISEL[4 -7]) are used to select a trigger source for a command FIFO.
SIU_ISEL select registers [4:5] are used to select a trigger source for command FIFOs in one eQADC.
SIU_ISEL select registers [6:7] are used to select a trigger source for command FIFOs in a second
eQADC. The cTSEL (combined Trigger Select) field is used to configure one of many possible trigger
sources for each command FIFO.
To trigger the eQADC, the trigger source must change to the state that the input to the command FIFO has
been programmed to recognize. A command FIFO trigger input can be programmed to recognize either
rising or falling edges, and low or high gated trigger types.
SIU_ISEL4: eTRIG_A[5:2]
Address: SIU_BASE + 0x0910
Access: R/ W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
cTSEL5_0
cTSEL4_0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
cTSEL3_0
cTSEL2_0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7-46
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor