PXR40RM Datasheet, PDF (344/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Interrupts and Interrupt Controller (INTC)
whose ISR presently is executing. This negating of a peripheral interrupt request outside of its ISR can be
a desired effect.
10.5.9.2 Negating Multiple Interrupt Requests in One ISR
An ISR can clear other flag bits besides its own flag bit. One reason that an ISR clears multiple flag bits
is because it serviced those other flag bits, and therefore the ISRs for these other flag bits do not need to
be executed.
10.5.9.3 Proper Setting of Interrupt Request Priority
Whether an interrupt request negates outside of its own ISR due to the side effect of an ISR execution or
the intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests
for these other flag bits must be selected properly. Their PRIn values in INTC priority select registers
(INTC_PSR0–INTC_PSR479) must be selected to be at or lower than the priority of the ISR that cleared
their flag bits. Otherwise, those flag bits still can cause the interrupt request to the processor to assert.
Furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to
INTC end-of-interrupt register (INTC_EOIR) as the clearing of the flag bit that caused the present ISR to
be executed. Refer to Section 10.4.3.1.2, End-of-Interrupt Exception Handler, for more information.
A flag bit whose enable bit or mask bit is negating its peripheral interrupt request can be cleared at any
time, regardless of the peripheral interrupt request’s PRIn value in INTC_PSRn.
10.5.10 Examining LIFO contents
Normally you do not need to know the contents of the LIFO, or even how deep the LIFO is nested.
Although the LIFO contents are not memory mapped, you can read the contents by popping the LIFO and
reading the PRI field in the INTC current priority register (INTC_CPR). Disabling processor recognition
of interrupts while examining the LIFO contents provides a coherent view of the preempted priorities.
The code sequence is:
pop_lifo:
store to INTC_EOIR
load INTC_CPR, examine PRI, and store onto stack
if PRI is not zero or value when interrupts were enabled, branch to pop_lifo
When you are finished examining the LIFO contents, you can restore it in software vector mode using the
following code sequence. In hardware vector mode, reading the INTC_IACKR does not push the
INTC_CPR[PRI] onto the LIFO, therefore the LIFO contents cannot be restored in hardware vector mode.
push_lifo:
load stacked PRI value and store to INTC_CPR
load INTC_IACKR
if stacked PRI values are not depleted, branch to push_lifo
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor