PXR40RM Datasheet, PDF (312/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Interrupts and Interrupt Controller (INTC)
written to the INTC_EOIR are ignored. Those values and sizes written to this register neither update the
INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes
of all 0’s to the INTC_EOIR.
Reading the INTC_EOIR has no effect on the LIFO.
Address: Base + 0x0018 (INTC_EOIR)
Access: W/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
EOIR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 10-11. INTC End-of-Interrupt Register (INTC_EOIR)
10.3.1.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0–7)
The INTC_SSCIRn support the setting or clearing of software configurable interrupt requests. These
registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. With
the exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral.
This flag bit generates an interrupt request within the INTC just like a peripheral interrupt request. Writing
a 1 to SETn leaves SETn unchanged at 0 but sets CLRn. Writing a 0 to SETn has no effect. CLRn is the
flag bit. Writing a 1 to CLRn clears it. Writing a 0 to CLRn has no effect. If a 1 is written to a pair SETn
and CLRn bits at the same time, CLRn is asserted, regardless of whether CLRn was asserted before the
write.
Although INTC_SSCIn is 8 bits wide, it can be accessed with a single 16-bit or 32-bit access, provided
that the access does not cross a 32-bit boundary.
Address: Base + 0x0020 + n (INTC_SSCIRn); n = 0–7
Access: R/W
R
W
Reset
0
1
2
3
4
5
6
0
0
0
0
0
0
0
SETn
0
0
0
0
0
0
0
Figure 10-12. INTC Software Set/Clear Interrupt Register (INTC_SSCIRn)
7
CLRn
0
Table 10-6. INTC_SSCIRn Field Descriptions
Field
0–5
6
SETn
7
CLRn
Description
Reserved, must be cleared.
Set flag bits. Writing a 1 sets the corresponding CLRn bit. Writing a 0 has no effect. Each SETn is always read as a 0.
Clear flag bits. CLRn is the flag bit. Writing a 1 to CLRn clears it provided that a 1 is not written simultaneously to its
corresponding SETn bit. Writing a 0 to CLRn has no effect.
0 Interrupt request not pending within INTC.
1 Interrupt request pending within INTC.
10-12
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor