PXR40RM Datasheet, PDF (523/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Periodic Interrupt Timer (PIT_RTI)
6. At the programmed RTI time interval, the RTI timer triggers an interrupt that is serviced by the
interrupt controller. (The interrupt controller is not put in low power mode by the SIU_HALT
register.) This interrupt also re-enables the CPU clock so that full CPU operation is restored.
7. In the RTI interrupt handler, the SIU_HALT register may be modified to restore operation as
desired. In some cases where periodic operation is preferred, the interrupt handler may perform a
set of tasks, and then write the SIU_HALT register mask and re-enter the low power mode by
executing the ‘msync’, ‘isync’, and ‘wait’ instructions again. The next RTI timeout repeats the
process.
NOTE
The RTI is a convenient mechanism for waking up the CPU in a controlled state once placed in low power
mode. However, the CPU will also exit low power mode under any of the following conditions:
• Any external interrupt from interrupt controller
• Critical interrupt
• NMI event
• Core watchdog timeout
• Core fixed interval timeout
• Core decrementer timeout
• Various debug events
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
20-11