PXR40RM Datasheet, PDF (762/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
EMIOS_CCR/Mode
•••
Channel Controller
MOD•En_en
••
MODE1_en
MODE0_en
Mode 0
Logic
Mode 1
Logic
•
••
Mode n
Logic
Control
Signals
Control Signals
Control Signals
••
••
•
Shared
Logic
Channel
Datapath
Figure 23-12. Unified Channel Control Block Diagram
23.4.1.1 Unified Channel Modes of Operation
The mode of operation of the unified channel is determined by the mode select bits MODE in the
EMIOS_CCR[n] register (see Table 23-9 for details).
When entering an output mode (except for GPIO mode), the output flip-flop is set to the complement of
the EDPOL bit in the EMIOS_CCR[n] register.
As the internal counter EMIOS_CCNTR[n] continues to run in all modes (except for GPIO mode), it is
possible to use this as a time base if the resource is not used in the current mode.
In order to provide smooth waveform generation even if A and B registers are changed on the fly, the
MCB, OPWFMB, OPWMB and OPWMCB modes are available. In these modes, the A and B registers
are double-buffered. These modes are presented in separate sections since basic differences exist between
these modes and the MC, OPWFM, OPWM, and OPWMC modes, respectively.
23.4.1.1.1 General-Purpose Input/Output (GPIO) Mode
In GPIO mode, all input capture and output compare functions of the unified channel are disabled, the
internal counter (EMIOS_CCNTR[n] register) is cleared and disabled. All control bits remain accessible.
In order to prepare the unified channel for a new operation mode, writing to registers EMIOS_CADR[n]
or EMIOS_CBDR[n] stores the same value in registers A1/A2 or B1/B2, respectively.
23-22
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor