PXR40RM Datasheet, PDF (568/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
eDMA
SRAM
Transfer control descriptor
(TCD)
Slave write address
Slave write data
SRAM
TCD0
eDMA engine
Bus read data
Data path
Bus write data
Bus address
Program model/
channel arbitration
Address
path
Control
TCDn – 1*
Slave read data
*n = 32 (64 for eDMA_A) channels
eDMA peripheral eDMA done
request
Figure 21-27. eDMA Operation, Part 3
21.5 Initialization / Application Information
21.5.1 eDMA Initialization
A typical initialization of the eDMA has the following sequence:
1. Write the EDMA_x_MCR if a configuration other than the default is desired.
2. Write the channel priority levels into the EDMA_x_CPRn registers if a configuration other than
the default is desired.
3. Enable error interrupts in the EDMA_x_EEIRL and/or EDMA_x_EEIRH registers if desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the EDMA_x_ERQRH and/or EDMA_x_ERQRL
registers.
6. Request channel service by software (setting the EDMA_x_TCD.START bit) or by hardware
(slave device asserting its DMA peripheral request signal).
21-44
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor