PXR40RM Datasheet, PDF (55/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Introduction
— Performs source and destination address calculations
— Performs data movement operations
• Includes SRAM-based memory containing the transfer control descriptors (TCD) for the channels.
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses, transfer size, plus support for enhanced
addressing modes
• TCD organized to support two-deep, nested transfer operations
• An inner data transfer loop defined by a “minor” byte transfer count
• An outer data transfer loop defined by a “major” iteration count
• Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
• One interrupt per channel, optionally asserted at completion of major iteration count
• Error termination interrupts are optionally enabled
• Support for scatter/gather DMA processing
• Channel transfers can be suspended by a higher priority channel
• Nexus data trace support on each DMA
1.2.17 Crossbar switch (XBAR)
The following summarizes the PXR40’s implementation of the crossbar switch:
• Supports simultaneous connections between master ports and slave ports (each master must access
a different slave)
• Supports a 32-bit address bus width and a 64-bit data bus width
• Six master ports:
— e200z7 core complex (two ports)
— eDMA2 module A
— eDMA2 module B
— FlexRay
— Nexus debug interface (NDI)
• Four slave ports
— Flash memory
— SRAM
— Peripheral bridge A
— Peripheral bridge B
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
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