PXR40RM Datasheet, PDF (198/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
SIU_IREER or SIU_IFEER registers for an IRQ and an IRQ edge-event occurs and is detected, the IRQ
flag bit is set in the SIU_EISR. The IRQ flag bits are cleared by writing a 1 to the bit. A write of 0 has no
effect.
The IRQ flag bit is set regardless of the state of the DMA or interrupt request enable bit in SIU_DIRER.
The IRQ flag bit remains set until cleared by software or through the servicing of a DMA or interrupt
request.
Address: SIU_BASE + 0x0014
Access: R/w1c
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R NMI 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EIF15 EIF14 EIF13 EIF12 EIF11 EIF10 EIF9 EIF8 EIF7 EIF6 EIF5 EIF4 EIF3 EIF2 EIF1 EIF0
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-5. External Interrupt Status Register (SIU_EISR)
The following table describes the fields in the external interrupt status register:
Table 7-11. SIU_EISR Bit Field Descriptions
Field
Description
0
NMI
1–15
16–31
EIFn
Non-Maskable Interrupt Flag. This bit is set when a NMI interrupt occurs on the NMI input pin. Cleared by writing a 1.
0 No NMI event has occurred on the NMI input
1 An NMI event has occurred on the NMI input
Reserved
External interrupt request flag n. This bit is set when an edge-triggered event occurs on the corresponding IRQ[n]
input. Cleared by writing a 1.
0 No edge-triggered event has occurred on the corresponding IRQ[n] input.
1 An edge-triggered event has occurred on the corresponding IRQ[n] input.
7.3.1.5 DMA/Interrupt Request Enable Register (SIU_DIRER)
The SIU_DIRER asserts a DMA transfer or external interrupt request if the IRQ flag bit is set in the
SIU_EISR. The DMA transfer or external interrupt request enable bits (EIRE flags) enable an external
interrupt request or DMA transfer request. The SIU uses one interrupt request to the interrupt controller.
The EIRE bits determine the external interrupt requests that assert the SIU interrupt request to the interrupt
controller.
7-16
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor