PXR40RM Datasheet, PDF (750/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
Field
0–31
Fn
Table 23-5. EMIOS_GFR Field Descriptions
Description
FLAG Bits. The EMIOS_GFR is a read-only register that groups the FLAG bits from all channels. These bits are
mirrors of the FLAG bits of each channel register (EMIOS_CSR[n]).
23.3.2.3 eMIOS200 Output Update Disable Register (EMIOS_OUDR)
Offset: EMIOS_BASE + 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
OU31 OU30 OU29 OU28 OU27 OU26 OU25 OU24 OU23 OU22 OU21 OU20 OU19 OU18 OU17 OU16
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
R
OU15 OU14 OU13 OU12 OU11 OU10 OU9
W
Reset 0
0
0
0
0
0
0
23
OU8
0
24
OU7
0
25
OU6
0
26
OU5
0
27
OU4
0
28
OU3
0
29
OU2
0
30
OU1
0
31
OU0
0
Figure 23-4. eMIOS200 Output Update Disable Register (EMIOS_OUDR)
Table 23-6. EMIOS_OUDR Field Descriptions
Field
0–31
OUn
Description
Channel [n] Output Update Disable Bits. When running MC, MCB, or an output mode, values are written to
registers A2 and B2. OUn bits are used to disable transfers from registers A2 to A1 and B2 to B1. Each bit controls
one channel.
0 Transfer enabled. Depending on the operation mode, transfer may occur immediately or in the next period.
Unless stated otherwise, transfer occurs immediately.
1 Transfers disabled.
23.3.2.4 eMIOS200 A Register (EMIOS_CADR[n])
Offset: UC[n] base address + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
W
A[0:23]
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
A[0:23]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-5. eMIOS200 A Register (EMIOS_CADR[n])
Depending on the mode of operation, internal registers A1 or A2, used for matches and captures, can be
assigned to address EMIOS_CADR[n]. A1 and A2 are cleared by reset. Table 23-7 summarizes the
EMIOS_CADR[n] writing and reading accesses for all operation modes. For more information see
Section 23.4.1.1, Unified Channel Modes of Operation.
23-10
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor