PXR40RM Datasheet, PDF (1277/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
Table 30-9. EBI_CAL_BR0-3 Descriptions (continued)
Field
Description
29
SETA
30
BI
31
V
Select External Transfer Acknowledge
The SETA bit controls whether accesses for this chip select will terminate (end transfer without error) based on
externally asserted D_TA or internally asserted D_TA. SETA should only be set when the BI bit is 1 as well, since
burst accesses with SETA=1 are not supported. Setting SETA=1 causes the BI bit to be ignored (treated as 1, burst
inhibited).
0 Transfer Acknowledge (D_TA) is an output from the EBI, data phase will be terminated by the EBI.
1 Transfer Acknowledge (D_TA) is an input to the EBI, data phase will be terminated by an external device.
Burst Inhibit
This bit determines whether or not burst read accesses are allowed for this chip-select bank. The BI bit is ignored
(treated as 1) for chip-select accesses with external D_TA (SETA=1).
0 Enable burst accesses for this bank.
1 Disable burst accesses for this bank. This is the default value out of reset (or when SETA=1).
Valid bit
The user writes this bit to indicate that the contents of this Base Register and Option Register pair are valid. The
appropriate CS signal does not assert unless the corresponding V-bit is set.
0 This bank is not valid.
1 This bank is valid.
30.3.1.5 EBI Option Registers (EBI_CAL_OR0-3)
Offset: EBI_BASE+0x44, 0x4C, 0x54, 0x5C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
AM¹
W
RESET: 1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
AM
W
SCY
0
0
BSCY
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 _{AM[0:2] is set to a fixed value of 0b111.}
Figure 30-6. EBI Option Registers (EBI_CAL_OR0-3)
The EBI Option Registers are used to define the address mask and other attributes for the corresponding
chip select.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
30-15