PXR40RM Datasheet, PDF (196/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
Table 7-8. SIU_RSR Bit Field Descriptions (continued)
Field
Description
29–30
BOOTCFG
Reset configuration pin status.
BOOTCFG[0:1] identifies the address of the reset configuration halfword (RCHW) and whether arbitration is used
by the boot assist module (BAM).
00 Internal boot mode – lowest address (0x0000_0000) from one of the six LAS fields in internal flash memory. 01
Serial boot mode – lower halfword of the censorship control word.
10 External boot mode – lowest address (0x0000_0000) of external memory as defined by the chip select 0
(D_CS[0]) signal with no external arbitration.
11 External boot mode with external arbitration.
31
RGF
Reset glitch flag.
Set by the reset controller when a glitch is detected on the RESET pin. This bit is cleared by the assertion of the
power-on reset input to the reset controller, or a write of 1 to the RGF bit. Refer to Section 7.4.2.2, RESET Pin
Glitch Detect, for more information on glitch detection.
0 No glitch has been detected on the RESET pin.
1 A glitch has been detected on the RESET pin.
Except for a POR request or writing a 1 to the software external reset flag (SERF) bit, all reset requests,
regardless of priority are not serviced until the current reset completes.
In the following cases, more than one reset bit is set in the reset status register (SIU_RSR):
Table 7-9. Causes That Set Multiple Reset Status Bits
Case 1
Condition
• POR request negates and the device remains in the reset
• External reset requested
• POR and external reset status bits are set
Reason POR request started the reset sequence, but an external reset request was received before the POR reset
sequence ended.
Case 2
Condition • Software external reset requested
• SERF flag bit set but no previously set bits in the SIU_RSR are cleared
Reason The SERF flag bit is cleared by writing a 1 (write 1 to clear) to the bit location or when another reset source
is asserted.
Case 3
Condition
• Loss-of-clock reset requested
• Loss-of-lock reset requested
• Watchdog reset requested
Reason More than one reset request occurred on the same clock cycle with no reset request by a higher-priority
reset source, therefore the status bits for all the requesting resets are set. Refer to Table 7-7.
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PXR40 Microcontroller Reference Manual, Rev. 1
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