PXR40RM Datasheet, PDF (946/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
If the application initiates a LIN TX frame transfer, i.e the TD bit is set to 1, the content and usage shown
in LIN Transmit Register (eSCI_LTR) - LIN TX frame generation applies. The initiation and transmit of
a TX frame is described in Section 26.4.6.3, LIN TX Frame generation.
If the application initiates an LIN RX frame, i.e the TD bit is set to 0, the content and usage shown in LIN
Transmit Register (eSCI_LTR) - LIN RX frame generation applies. The initiation and transmit of a RX
frame is described in Section 26.4.6.4, LIN RX frame generation.
Each write access to this register increments the internal write access counter and enables the writing to
the next field. The write access counter is reset if
• the LIN PE is in the idle state (eSCI_LCR1[LRES] = 1)
• a LIN TX frame was completely transmitted (eSCI_IFSR1[FRC] was set to 1)
• a LIN RX frame was completely received (eSCI_IFSR1[FRC] was set to 1)
• module has entered Stop Mode.
Table 26-14. eSCI_LTR Field Descriptions
Field
P
ID
Description
Identifier Parity. This field provides the identifier parity which is used to create the protected identifier if the
automatic identifier parity generation is disabled, i.e the PRTY bit in LIN Control Register 1 (eSCI_LCR1) is 0.
Identifier. This field is used for the identifier field in the protected identifier.
LEN
Frame Length. This field defines the number of data bytes to be transmitted or received.
CSM
CSE
CRC
TD
TO
D
Checksum Model. This bit controls the checksum calculation model used.
0 Classic Checksum Model (LIN 1.3).
1 Enhanced Checksum Model (LIN 2.0).
Checksum Enable. This bit control the generation and checking of the checksum byte.
0 No generation and checking of checksum byte.
1 Generation and checking of checksum byte.
CRC Enable. This bit controls the generation of checking standard or enhanced LIN frames, which are described
in Section 26.4.6.2, LIN frame formats.
0 Standard LIN frame generation and checking.
1 Enhanced LIN frame generation and checking.
Transfer Direction. This bit control the transfer direction of the data, crc, and checksum byte fields.
0 Data, CRC, and Checksum byte fields received, described in Section 26.4.6.4, LIN RX frame generation.
1 Data, CRC, and Checksum byte fields transmitted, described in Section 26.4.6.3, LIN TX Frame generation.
Timeout Value. The content of the field depends on the transfer direction.
RX frame: Defines the time available for a complete RX frame transfer, as described in Section 26.4.6.5.4, Fast
Bit Error Detection.
TX frame: Must be set to 0.
Transmit Data. Data bits for transmission.
26-18
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor