PXR40RM Datasheet, PDF (373/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Flash Memory Array and Control
19–20
WWSC
Table 12-12. FLASH_BIUCR Field Descriptions
Write Wait State Control - This field is used to control the number of wait-states to be added to the
best-case flash array access time for writes. The best-case flash array access time for writes is two cycles.
This field must be set to a value corresponding to the operating frequency of the flash. Higher operating
frequencies require non-zero settings for this field for proper flash operation. This field is set to 0b11 by
hardware reset.
21–23
RWSC
00 No additional wait-states are added
01 One additional wait-state is added
10 Two additional wait-states are added
11 Three additional wait-states are added
Read Wait State Control - This field is used to control the number of wait-states to be added to the
best-case flash array access time for reads. The best-case flash array access time for reads is one cycle.
This field must be set to a value corresponding to the operating frequency of the flash and the actual read
access time of the flash. Higher operating frequencies require non-zero settings for this field for proper
flash operation.
24
25
DPFEN
26
27
IPFEN
28
29–30
PFLIM
31
BFEN
This field is set to 0b111 by hardware reset.
000 No additional wait-states are added
001 One additional wait-state is added
...
111 Seven additional wait-states are added
Note: The settings for APC and RWSC must be the same.
Note: Valid settings are specified in the product Data Sheet.
Reserved
Data Prefetch Enable - This field enables or disables prefetching initiated by a data read access. This field
is cleared by hardware reset.
0 No prefetching is triggered by a data read access
1 Prefetching may be triggered by any data read access
Reserved
Instruction Prefetch Enable - This bit enables or disables prefetching initiated by an instruction read
access. This field is cleared by hardware reset.
0 No prefetching is triggered by an instruction read access
1 Prefetching may be triggered by any instruction read access
Reserved
Flash Prefetch Limit - This field controls the prefetch algorithm used by the flash prefetch controller. This
field defines a limit on the maximum number of sequential prefetches which will be attempted between
buffer misses. In all situations when enabled, only a single prefetch is initiated on each buffer miss or hit.
This field is cleared by hardware reset.
00 No prefetching or buffering is performed.
01 The referenced line is prefetched on a buffer miss, i.e., prefetch on miss.
1x The referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer
hit (if not already present), i.e., prefetch on miss or hit.
Flash Line Read Buffers Enable - This bit enables or disables line read buffer hits. It is also used to
invalidate the buffers. This bit is cleared by hardware reset.
0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.
1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the
buffers are successfully filled.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
12-21