PXR40RM Datasheet, PDF (572/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
21.5.3 DMA Request Assignments
The assignments between the DMA requests from the modules to the channels of the two eDMAs are
shown in Table 21-24 and Table 21-24. The source column is written in C language syntax. The syntax is
module_instance.register[bit].
DMA Request
EQADC_A_FISR0_CFFF0
EQADC_A_FISR0_RFDF0
EQADC_A_FISR1_CFFF1
EQADC_A_FISR1_RFDF1
EQADC_A_FISR2_CFFF2
EQADC_A_FISR2_RFDF2
EQADC_A_FISR3_CFFF3
EQADC_A_FISR3_RFDF3
EQADC_A_FISR4_CFFF4
EQADC_A_FISR4_RFDF4
EQADC_A_FISR5_CFFF5
EQADC_A_FISR5_RFDF5
DSPIB_SR_TFFF
DSPIB_SR_RFDF
DSPIC_SR_TFFF
DSPIC_SR_RFDF
DSPID_SR_TFFF
DSPID_SR_RFDF
eSCIA_COMBTX
eSCIA_COMBRX
eMIOS_GFR_F0
eMIOS_GFR_F1
eMIOS_GFR_F2
eMIOS_GFR_F3
eMIOS_GFR_F4
Table 21-23. DMA Request Summary for eDMA_A
Channel
Source
0 EQADC_A.FISR0[CFFF0]
1 EQADC_A.FISR0[RFDF0]
2 EQADC_A.FISR1[CFFF1]
3 EQADC_A.FISR1[RFDF1]
4 EQADC_A.FISR2[CFFF2]
5 EQADC_A.FISR2[RFDF2]
6 EQADC_A.FISR3[CFFF3]
7 EQADC_A.FISR3[RFDF3]
8 EQADC_A.FISR4[CFFF4]
9 EQADC_A.FISR4[RFDF4]
10 EQADC_A.FISR5[CFFF5]
11 EQADC_A.FISR5[RFDF5]
12 DSPIB.SR[TFFF]
13 DSPIB.SR[RFDF]
14 DSPIC.SR[TFFF]
15 DSPIC.SR[RFDF]
16 DSPID.SR[TFFF]
17 DSPID.SR[RFDF]
18 ESCIA.SR[TDRE] ||
ESCIA.SR[TC] ||
ESCIA.SR[TXRDY]
19 ESCIA.SR[RDRF] ||
ESCIA.SR[RXRDY]
20 EMIOS.GFR[F0]
21 EMIOS.GFR[F1]
22 EMIOS.GFR[F2]
23 EMIOS.GFR[F3]
24 EMIOS.GFR[F4]
Description
EQADC_A Command FIFO 0 Fill Flag
EQADC_A Receive FIFO 0 Drain Flag
EQADC_A Command FIFO 1 Fill Flag
EQADC_A Receive FIFO 1 Drain Flag
EQADC_A Command FIFO 2 Fill Flag
EQADC_A Receive FIFO 2 Drain Flag
EQADC_A Command FIFO 3 Fill Flag
EQADC_A Receive FIFO 3 Drain Flag
EQADC_A Command FIFO 4 Fill Flag
EQADC_A Receive FIFO 4 Drain Flag
EQADC_A Command FIFO 5 Fill Flag
EQADC_A Receive FIFO 5 Drain Flag
DSPIB Transmit FIFO Fill Flag
DSPIB Receive FIFO Drain Flag
DSPIC Transmit FIFO Fill Flag
DSPIC Receive FIFO Drain Flag
DSPID Transmit FIFO Fill Flag
DSPID Receive FIFO Drain Flag
eSCIA combined DMA request of the Transmit Data
Register Empty, Transmit Complete, and LIN Transmit
Data Ready DMA requests
eSCIA combined DMA request of the Receive Data
Register Full and LIN Receive Data Ready DMA
requests
eMIOS channel 0 Flag
eMIOS channel 1 Flag
eMIOS channel 2 Flag
eMIOS channel 3 Flag
eMIOS channel 4 Flag
21-48
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor