PXR40RM Datasheet, PDF (797/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on A or B respectively. Note that FLAG bit is not set by the FORCMA and
FORCMB operations.
If subsequent matches occur on comparators A and B, the PWM pulses continue to be generated,
regardless of the state of the FLAG bit.
At OPWM mode entry, the output flip-flop is set to the complement of the EDPOL bit in the
EMIOS_CCR[n] register.
In order to achieve 100% duty cycle, both registers A1 and B1 must be set to the same value. When a
simultaneous match on comparators A and B occur, the output flip-flop is set at every period to the value
of EDPOL bit. 0% duty cycle is possible by writing 0x0 to register A (EMIOS_CADR). When a match
occurs, the output flip-flop is set at every period to the complement of EDPOL bit. The transfer from
register B2 to B1 is still controlled by MODE[6] bit.
NOTE
If A1 and B1 are set to 0x00_0000, a 0% duty cycle waveform is produced.
Figure 23-51 and Figure 23-52 show the unified channel running in OPWM with immediate update and
next period update, respectively.
MODE[6] = 0
Selected Counter Bus
0xFFFFFF
0x001000
0x000900
0x000200
Update to ^B2
A1
Write
A1 Match B1 Match
Update to
A1
A1 Match B1 Match
0x000000
Output Flip-Flop
A1 Value¹ 0xxxxxxx 0x000200
B1 Value 0xxxxxxx
B2 Value² 0xxxxxxx
0x001000 0x001000
0x001000
0x000900
0x000900
0x001000
Notes: 1. EMIOS_CADR[n] = A1
2. EMIOS_CBDR[n] = B2
A2 = A1 according to OU[n] bit
B2 = B1 according to OU[n] bit
Figure 23-51. OPWM with Immediate Update
Time
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-57