PXR40RM Datasheet, PDF (1334/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
Reg Index: 127
0
1
2
R
W
FPM
MCKO MCKO
_GT _EN
Reset 0
0
0
3
4
5
MCKO_DIV
0
0
0
Access: R/W
6
7
8
9
10 11 12 13 14
15
000000000
0
000000000
0
16
17
18
19
20
21
22 23 24 25 26 27 28 29 30
31
R
PSTAT
W
_EN
Reset 0
0
0
0
0
0 000000000
0
Figure 31-4. Port Configuration Register (PCR)
Table 31-11. PCR Field Descriptions
Field
Description
0
FPM
Full port mode. Determines if the auxiliary output port uses the full MDO port or a reduced MDO port to
transmit messages.
0 The subset of MDO[11:0] pins are used to transmit messages.
1 All MDO[15:0] pins are used to transmit messages.
Section 7.3.1.13, Pad Configuration Registers (SIU_PCR), shows how GPIO is enabled or disabled by the
FPM setting.
1
MCKO clock gating control. Enables or disables MCKO clock gating. If clock gating is enabled, the MCKO
MCKO_GT clock is gated when the NPC is in enabled mode but not actively transmitting messages on the auxiliary output
port. When clock gating is disabled, MCKO is allowed to run even if no auxiliary output port messages are
being transmitted.
0 MCKO gating is disabled.
1 MCKO gating is enabled.
2
MCKO enable. Enables the MCKO clock. When enabled, the frequency of MCKO is determined by the
MCKO_EN MCKO_DIV field.
0 MCKO clock is driven to zero.
1 MCKO clock is enabled.
3–5 MCKO division factor. Determines the frequency of MCKO relative to the system clock frequency when
MCKO_DIV MCKO_EN is asserted. The table below shows the meaning of MCKO_DIV values. In this table, SYS_CLK
represents the system clock frequency.
MCKO_DIV[2:0]
MCKO Frequency
0
SYS_CLK¹
1
SYS_CLK  2
2
Invalid value
3
SYS_CLK  4
4
Invalid value
5
Invalid value
6
Invalid value
7
SYS_CLK  8
1 _{The SYS_CLK setting for MCKO should only be used}
if this setting does not violate the maximum operating
frequency of the auxiliary port pins.
31-18
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor