PXR40RM Datasheet, PDF (980/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Table 26-36. eSCI Interrupt Flags and Interrupt Enable Bits
Interrupt Source Operational Mode Interrupt Flag Interrupt Enable Bit
Transmitter
Transmitter
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Transmitter
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Transmitter, Receiver
SCI
SCI, LIN
SCI
SCI
SCI
SCI, LIN
SCI, LIN
SCI
LIN
LIN
LIN
LIN
LIN
LIN
LIN
LIN
LIN
LIN
LIN
eSCI_IFSR1[TDRE] eSCI_CR1[TIE]
eSCI_IFSR1[TC]
eSCI_CR1[TCIE]
eSCI_IFSR1[RDRF] eSCI_CR1[RIE]
eSCI_IFSR1[IDLE] eSCI_CR1[ILIE]
eSCI_IFSR1[OR]
eSCI_CR2[ORIE]
eSCI_IFSR1[NF]
eSCI_CR2[NFIE]
eSCI_IFSR1[FE]
eSCI_CR2[FEIE]
eSCI_IFSR1[PF]
eSCI_CR2[PFIE]
eSCI_IFSR1[BERR] eSCI_CR2[BERRIE]
eSCI_IFSR2[RXRDY] eSCI_LCR1[RXIE]
eSCI_IFSR2[TXRDY] eSCI_LCR1[TXIE]
eSCI_IFSR2[LWAKE] eSCI_LCR1[WUIE]
eSCI_IFSR2[STO] eSCI_LCR1[STIE]
eSCI_IFSR2[PBERR] eSCI_LCR1[PBIE]
eSCI_IFSR2[CERR] eSCI_LCR1[CIE]
eSCI_IFSR2[CKERR] eSCI_LCR1[CKIE]
eSCI_IFSR2[FRC] eSCI_LCR1[FCIE]
eSCI_IFSR2[UREQ] eSCI_LCR2[URIE]
eSCI_IFSR2[OVFL] eSCI_LCR2[OFIE]
26.4.7.2 Interrupt Request Generation
The eSCI module provides one hardware interrupt request signal to the systems interrupt controller. This
interrupt request signal is asserted if and only if at least one of the interrupt flags and the corresponding
interrupt enables are set to 1. Otherwise the interrupt line is deasserted.
26.5 Application Information
26.5.1 SCI Data Frames Separated by Preamble
To separate SCI data frame with preambles with minimum idle line time, use this sequence between
messages:
1. write to SCI Data Register (ESCI_DR)
— this sets the internal iCMT bit which requests the data transmission
2. wait until TDRE in Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set
— this indicates the start of transmission; the iCMT bit was cleared
26-52
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor