PXR40RM Datasheet, PDF (1183/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
Table 29-2. Output Disable Channel Groups (continued)
eMIOS Channel
20
21
22
23
Engine
B
Channels
0 to 7
8 to 15
16 to 23
24 to 31
29.2.3 Memory Map/Register Definition
The guideline for the description of all bits and fields throughout this section is to provide only a brief
explanation (without examples or method of use) of the features, since it will be used mainly as a reference
for the reader that is studying Section 29.3, Functional Description, where those features are explained in
detail.
29.2.4 Memory Map
The eTPU System simplified memory map is shown in Table 29-4. Each of the register areas shown may
have their own reserved address areas.
Table 29-5 show detailed memory maps. Offsets are relative to the eTPU Base addresses given in
Table 29-3.
Table 29-3. eTPU Module Base Addresses
eTPU Module
A/B
Base address
0xC3FC_0000
SCM unused area is decoded and returns a fixed opcode defined in the register ETPUSCMOFFDATAR.
Table 29-4. High Level Memory Map
Offset
0x00-0x1F
0x20-0x2F
0x30-0x3F
0x40-0x4F
0x50-0x5F
0x60-0x6F
0x70-0x7F
0x80-0xFF
0x100-0x13F
0x140-0x1FF
0x200-0x2FF
0x300-0x3FF
0x400-0x7FF
0x800-0xBFF
0xC00-0xFFF
Use
System Configuration Registers
eTPU A Time Base Registers
Reserved¹
eTPU B Time Base Registers
Reserved¹
eTPU A Extra Engine Registers
eTPU B Extra Engine Registers
Reserved¹
Memory Error Support Registers
Reserved¹
eTPU A/B Global Channel Registers
Reserved¹
eTPU A Channel Registers
eTPU B Channel Registers
Reserved¹
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-15