PXR40RM Datasheet, PDF (1299/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
D_CLKOUT
D_ADD[9:30]
A
A+4
A+8
A + 0xc
D_RD_WR
D_BDIP
D_TS
D_ADD_DAT[0:31]
1
D_ADD_DAT is valid
2
*
D_ADD_DAT is valid
3
4**
D_ADD_DAT is valid
D_TA
CS[n]
D_WE
* ^{This extra cycle is required after accesses 2, 4, and 6 to get the next 64-bits of internal write data.}
** ^{Four more external accesses (not shown) are required to complete the internal 32-byte request.}
The timing of these is the same as accesses 1-4 shown in this diagram.
Figure 30-28. 32-Byte Write Cycle with External D_TA, Basic Timing
30.4.2.6.3 Small Access Example #3: 32-byte Read to 32-bit Port with BL=1
Figure 30-29 shows an example of a 32-byte read to a 32-bit burst enabled port with burst length of 4
words, requiring two 16-byte external transactions. For this case, the address for the 2nd 4-word burst
access is calculated by adding 0x10 to the lower 5 bits of the 1st address (no carry), and then masking out
the lower 4 bits to fix them at zero.
Table 30-15. Examples of 4-word Burst Addresses
1st Address
0x000
0x008
0x010
0x018
0x020
0x028
0x030
0x038
Lower 5 bits of 1st Address +
0x10 (no carry)
0x10
0x18
0x00
0x08
0x30
0x38
0x20
0x28
Final 2nd Address (After
Masking Lower 4 Bits)
0x10
0x10
0x00
0x00
0x30
0x30
0x20
0x20
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
30-37