PXR40RM Datasheet, PDF (384/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Flash Memory Array and Control
12.3.4.1 Software Locking
A software mechanism is provided to independently lock/unlock each high-, mid-, and low-address space
against program and erase.
Software locking is done through the FLASH_x_LMLR (low-/mid-address space block locking register),
FLASH_x_SLMLR (secondary low-/mid-address space block locking register), or FLASH_x_HLR
(high-address space block locking register). These can be written through register writes and read through
register reads.
When the program/erase operations are enabled through hardware, software locks are enforced through
doing register writes.
12.3.4.1.1 Flash Program Suspend/Resume
The program sequence may be suspended to allow read access to the flash core. It is not possible to erase
or program during a program suspend. Interlock writes should not be attempted during program suspend.
A program suspend can be initiated by changing the value of the FLASH_x_MCR[PSUS] bit from a 0 to
a 1. FLASH_x_MCR[PSUS] can be set high at any time when FLASH_x_MCR[PGM] and
FLASH_x_MCR[EHV] are high. A 0 to 1 transition of FLASH_x_MCR[PSUS] causes the flash module
to start the sequence to enter program suspend, which is a read state. The module is not suspended until
FLASH_x_MCR[DONE] = 1. At this time flash core reads may be attempted. After it is suspended, the
flash core may be read only. Reads to the blocks being programmed/erased return indeterminate data.
The program sequence is resumed by writing a logic 0 to FLASH_x_MCR[PSUS].
FLASH_x_MCR[EHV] must be set to a 1 before clearing FLASH_x_MCR[PSUS] to resume operation.
When the operation resumes, the flash module continues the program sequence from one of a set of
predefined points. This may extend the time required for the program operation.
12.3.5 Flash Erase
Erase changes the value stored in all bits of the selected blocks to logic 1. Locked or disabled blocks cannot
be erased. If multiple blocks are selected for erase during an erase sequence, the blocks are erased
sequentially starting with the lowest numbered block and terminating with the highest. Aborting an erase
operation will leave the flash core blocks being erased in an indeterminate data state. This can be recovered
by executing an erase on the affected blocks.
The erase sequence consists of the following sequence of events:
1. Change the value in the FLASH_x_MCR[ERS] bit from 0 to a 1.
2. Select the block, or blocks, to be erased by writing 1s to the appropriate registers in
FLASH_x_LMSR or FLASH_x_HSR. If the shadow row is to be erased, this step may be skipped,
and FLASH_x_LMSR and FLASH_x_HSR are ignored. For shadow row erase, see section
Section 12.3.6, Flash Shadow Block, for more information.
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor