PXR40RM Datasheet, PDF (899/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
• Trigger signal combined with a change in data
The four transfer initiation conditions are described in Section 25.4.4.5, DSI Transfer Initiation Control.
Transfer attributes are set during initialization. The DSICTAS field in the DSPI_DSICR determines which
of the DSPI_CTAR registers will control the transfer attributes.
25.4.4.2 DSI Slave Mode
In DSI Slave Mode the DSPI responds to transfers initiated by a SPI or DSI bus master. In this mode the
DSPI does not initiate DSI transfers. Certain transfer attributes such as clock polarity and phase must be
set for successful communication with a DSI master. The DSI Slave Mode Transfer attributes are set in the
DSPI_CTAR1.
If the CID bit in the DSPI_DSICR is set and the data in the DSPI_COMPR differs from the selected source
of the serialized data, the slave DSPI will assert the MTRIG signal. If the slave’s HT signal is asserted and
the TRRE is set, the slave DSPI asserts MTRIG. These features are included to support chaining of several
DSPI. Details about the MTRIG signal is found in Section 25.4.4.6, Multiple Transfer Operation (MTO).
25.4.4.3 DSI Serialization
In the DSI Configuration from four to sixteen bits can be serialized using two different sources. The TXSS
bit in the DSPI_DSICR selects between the DSPI DSI Serialization Data Register (DSPI_SDR) and the
DSPI DSI Alternate Serialization Data Register (DSPI_ASDR) as the source of the serialized data. The
DSPI_SDR holds the latest Parallel Input signal values which is sampled at every rising edge of the system
clock. The DSPI_ASDR register is written by host software and used as an alternate source of serialized
data.
A copy of the last 32-bit DSI frame shifted out of the Shift Register is stored in the DSPI DSI Transmit
Comparison Register (DSPI_COMPR). This register provides added visibility for debugging and it serves
as a reference for transfer initiation control. Figure 25-20 shows the DSI Serialization logic.
Slave Bus Interface
DSPI Alternate
Serialization Data Register
32
DSI Serialization
Data Register
DSI Config.
Register
DSI Transmit
Comparison Register
Clock
Logic
32
Parallel ³²
Inputs
1
0
32
01
15
1 ¹⁶
0
Shift Register
Control
Logic
Figure 25-20. DSI Serialization Diagram
SCK
SOUT
PCS
HT
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-39