PXR40RM Datasheet, PDF (985/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
27.2 Block Diagram
Figure 27-2 is the block diagram for an EQADC block (Table 27-1 describes the main sub-blocks).
AN0/DAN0+
AN1/DAN0-
AN2/DAN1+
AN3/DAN1-
AN4/DAN2+
AN5/DAN2-
AN6/DAN3+
AN7/DAN3-
AN8/ANW
AN9/ANX/TBIAS
AN10/ANY
AN11/ANZ
AN12/T50PVREF
AN13/T25PVREF
AN14/T75PVREF
AN15
AN16/ANR
AN17/ANS
AN18/ANT
AN19/ANU
AN20-39
REFBYPC
MA0
MA1
MA2
EQADC
ADC0
FIL
ETRIGx,ATRIG
BYPASSx
ADC Control
Logic
FIFO Control
Unit
CBuffer0
Abort
Cont
CFIFOx
32 bits
REF BIAS
GEN GEN
Result
Format
and
Calibra-
tion
ADC1
CBuffer1
Abort
Cont
Pre-Charge
RFIFOx
16 bits
MUX
Control
Logic
Channel
Number
System
Memory
CQueue y
RQueue y
DMA and
Interrupt
Requests
DMA Transaction
Done Signals
VDDA
VSSA
VRH
VRL
EQADC
Parallel Side Interface
(EQADC PSI)
On-Chip
Digital Signal Processor
(Decimation Filter)
Figure 27-2. EQADC Block Diagram
NOTE: x=0, 1, 2, 3, 4, 5
y=0, 1, 2, 3, ...
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-3