PXR40RM Datasheet, PDF (909/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
25.4.7 Transfer Formats
The SPI serial communication is controlled by the Serial Communications Clock (SCK) signal and the
PCS signals. The SCK signal provided by the Master device synchronizes shifting and sampling of the data
on the SIN and SOUT pins. The PCS signals serve as enable signals for the slave devices.
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI Clock and Transfer Attributes
Registers (DSPI_CTARx) select the polarity and phase of the serial clock, SCK. The polarity bit selects
the idle state of the SCK. The clock phase bit selects if the data on SOUT is valid before or on the first
SCK edge.
When the DSPI is the bus Slave, CPOL and CPHA bits in the DSPI_CTAR0 (SPI) or DSPI_CTAR1 (DSI)
select the polarity and phase of the serial clock. For SPI Slaves the DSPI_CTAR0 is used, and for DSI
Slaves the DSPI_CTAR1 is used. Even though the bus Slave does not control the SCK signal, clock
polarity, clock phase and number of bits to transfer must be identical for the master device and the slave
device to ensure proper transmission.
The DSPI supports four different transfer formats:
• Classic SPI with CPHA=0
• Classic SPI with CPHA=1
• Modified Transfer format with CPHA = 0
• Modified Transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The MTFE bit in the DSPI_MCR selects between Classic SPI
Format and Modified Transfer Format. The Classic SPI Formats are described in Section 25.4.7.1, Classic
SPI Transfer Format (CPHA = 0), and Section 25.4.7.2, Classic SPI Transfer Format (CPHA = 1). The
Modified Transfer Formats are described in Section 25.4.7.3, Modified SPI/DSI Transfer Format (MTFE
= 1, CPHA = 0), and Section 25.4.7.4, Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1).
In the SPI and DSI Configurations, the DSPI provides the option of keeping the PCS signals asserted
between frames. See Section 25.4.7.5, Continuous Selection Format, for details.
25.4.7.1 Classic SPI Transfer Format (CPHA = 0)
The transfer format shown in Figure 25-29 is used to communicate with peripheral SPI slave devices
where the first data bit is available on the first clock edge. In this format, the master and slave sample their
SIN pins on the odd-numbered SCK edges and change the data on their SOUT pins on the even-numbered
SCK edges.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-49