PXR40RM Datasheet, PDF (334/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Interrupts and Interrupt Controller (INTC)
10.4.3.1.2 End-of-Interrupt Exception Handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be
written. When it is written, the LIFO is popped so that the preempted priority is restored into PRI of the
INTC_CPR. Before it is written, the peripheral or software configurable flag bit must be cleared so that
the peripheral or software configurable interrupt request is negated.
NOTE
To ensure proper operation across all Power Architecture MCUs, execute an
MBAR or MSYNC instruction between the access to clear the flag bit and the
write to the INTC_EOIR.
When returning from the preemption, the INTC does not search for the peripheral or software configurable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request can no longer be asserted. When PRI in INTC_CPR is lowered to the priority of the preempted
ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software configurable
interrupt request at or below that priority does not cause a preemption. Instead, after the restoration of the
preempted context, the processor returns to the instruction address that it was to next execute before it was
preempted. This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog
or epilog.
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt Vector
0
Interrupt
Acknowledge
Read
INTC_IACKR
Write
INTC_EOIR
INTVEC in
INTC_IACKR
0
108
PRI in
INTC_CPR
0
1
0
Peripheral Interrupt
Request 100
Figure 10-14. Software Vector Mode Handshaking Timing Diagram
10.4.3.2 Hardware Vector Mode Handshaking
A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in Figure 10-15. As in
software vector mode, the INTC examines the peripheral and software configurable interrupt requests, and
when it finds an asserted one with a higher priority than PRI in INTC_CPR, it asserts the interrupt request
10-34
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor