PXR40RM Datasheet, PDF (262/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
logically ORed, which provides the potential for combining outputs from multiple timer channels and data
registers to produce more complex bit behavior.
SIU_BASE + 0xD40
R
W
RESET:
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB ETPUB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-33. eTPU_B Select Register for DSPI_A (SIU_ETPUBA)
Table 7-54. SIU_ETPUBA Field Descriptions
Field
Description
0–31
ETPUB channel select
ETPUBx 0 This bit in the DSPI_A serialized output frame will not use the respective ETPUB channel
1 This bit in the DSPI_A serialized output frame will use the respective ETPUB channel
SIU_BASE + 0xD44
R
W
RESET:
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
7
6
5
4
3
2
1
0
8
9 10 11 12 13 14 15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
16 17 18 19 20 21 22 23 0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-34. eMIOS Select Register for DSPI_A (SIU_EMIOSA)
Table 7-55. SIU_EMIOSA Field Descriptions
Field
Description
0–31
EMIOS channel select
EMIOSx 0 This bit in the DSPI_A serialized output frame will not use the respective EMIOS channel
1 This bit in the DSPI_A serialized output frame will use the respective EMIOS channel
7-80
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor