PXR40RM Datasheet, PDF (1156/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
• Take the Head to freeze or low-power first, wait for DECFILTER_x_MSR bit BSY=0, and repeat
the procedure for the other blocks in the chain in sequence, towards the Tail block.
Take the blocks out of freeze or low-power modes in the inverse sequence, from Tail to Head.
28.3.15 Enhanced Debug Monitor Description
This feature is enabled by the EDME bit in the configuration register DECFILTER_x_MCR. The
monitoring operation is applicable only to an eQADC input data source, and applies when filters are
cascaded. The Enhanced Debug Monitor feature makes the input sample data also available in the
DECFILTER_x_EDID register. A DMA or interrupt request (selected by DECFILT_x_MCR[DSEL])
indicates a new input was fed and DECFILTER_x_EDID was updated. The input is processed normally
by the filter.
An Enhanced Debug Input Data Register (DECFILTER_x_EDID) overrun can occur if a sample is not
read by the CPU or DMA before overwritten by a new sample. The overrun is indicated in a separate flag
DIVR in the status register DECFILTER_x_MSR. If the ERREN bit is set in the DECFILTER_x_MCR
configuration register, this overrun asserts the an interrupt request.
28.4 Application Information
The following sections describe common use cases and configurations of the decimation filter block.
28.4.1 eQADC Configuration for Decimation Filter Operation
28.4.1.1 eQADC Configuration / Decimation Filter Input
In normal mode of operation of the Decimation Filter, filter data inputs are supplied by an eQADC block
and the filter output is returned to the specified RFIFO in the eQADC. In standard eQADC operation,
conversion results are routed directly from the converter to one of the local eQADC RFIFO buffers.
However, by using alternate conversion command word configurations in the eQADC, conversion results
can be routed to the Decimation Filter block. Additionally, the same eQADC conversion results can be
routed to a second Decimation Filter block specified by an Extended Alternate Configuration register. The
eQADC can send either conversion data or timestamp data. The conversion data is filtered by the
decimation filter and the timestamp is bypassed and delayed until ready to be sent back to the eQADC
when the relevant conversion data is filtered and available.
In the eQADC, the ALT_CONFIG_SEL[0:7] field of the Conversion Command Word (CCW) specifies
whether an alternate configuration is used for the ADC conversion. The values for this field are given in
Table 28-17. The eQADC can store up to eight alternate configurations, which can be dynamically selected
during the ADC conversion with the CCW. When the ALT_CONFIG_SEL field is set to 0x00, no alternate
configuration is used, and the ADC conversion is processed according to the CCW.
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor