PXR40RM Datasheet, PDF (1121/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
Table 28-3. Block Memory Map (continued)
Address
Register
Bits Access Reset Value Section/Page
DECFILT_x_ BASE + DECFILTER_TAP6 — Filter TAP 6 Register
0x090
32
R 0x0000_0000 28.2.2.8/28-21
DECFILT_x_ BASE + DECFILTER_TAP7 — Filter TAP 7 Register
0x094
32
R 0x0000_0000 28.2.2.8/28-21
DECFILT_x_ BASE + Reserved
0x098–0x0CF
DECFILT_x_ BASE + DECFILTER_EDID — Enhanced Debug Input 32
0x0D0
Data
R 0x0000_0000 28.2.2.9/28-22
DECFILT_x_ BASE + Reserved
0x0D4–0x0DF
DECFILT_x_ BASE + DECFILTER_FINTVAL — Final Integration Value 32
0x0E0
Register
R 0x0000_0000 28.2.2.10/28-23
DECFILT_x_ BASE + DECFILTER_FINTCNT — Final Integration
0x0E4
Count Register
32
R 0x0000_0000 28.2.2.11/28-23
DECFILT_x_ BASE + DECFILTER_CINTVAL — Current Integration
32
R 0x0000_0000 28.2.2.12/28-24
0x0E8
Value Register
DECFILT_x_ BASE + DECFILTER_CINTCNT — Current Integration 32
0x0EC
Count Register
R 0x0000_0000 28.2.2.13/28-24
DECFILT_x_ BASE + Reserved
0x0F0–0x1FF
1 _{The TAP register stores, on each filter node, the input sample data and, for the IIR type, the filter intermediary results.}
28.2.2 _{Decimation Filter Register Descriptions}
All registers are 32-bit wide, and each of the eight Decimation Filters on the device have the same register
interface.
28.2.2.1 Decimation Filter Module Configuration Register (DECFILT_x_MCR)
The Decimation Filter module configuration register provides configuration control bits for the
Decimation Filter internal logic.
NOTE
Do not modify this register’s contents when the status bit BSY is set, except
for fields FREN, FRZ and IDIS. To guarantee that BSY does not set during
the read-modify-write operation, it is advisable to set IDIS=1 and wait for
BSY=0 beforehand.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-7