PXR40RM Datasheet, PDF (424/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
Table below lists register settings when a FIT interrupt is taken.
Table 13-26. Fixed-Interval Timer Interrupt—Register Settings
Register
Setting Description
SRR0
SRR1
MSR
ESR
MCSR
DEAR
Vector
Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
Set to the contents of the MSR at the time of the interrupt
UCLE 0
SPE 0
WE 0
CE —
EE 0
PR 0
FP 0
ME —
FE0 0
DE —
FE1 0
IS 0
DS 0
PMM 0
RI —
Unchanged
Unchanged
Unchanged
IVPR_0:15 || IVOR11_16:27 || 4b0000
13.9.13 Watchdog Timer Interrupt (IVOR12)
The triggering of the exception is caused by the first enabled watchdog time-out.
A Watchdog Timer interrupt occurs when no higher priority exception exists, a Watchdog Timer exception
exists (TSR_WIS=1), and the interrupt is enabled (both TCR_WIE and MSR_CE=1).
The Timer Status Register (TSR) holds the Watchdog interrupt bit set by the Timer facility when an
exception is detected. Software must clear this bit in the interrupt handler to avoid repeated Watchdog
interrupts.
Table below lists register settings when a Watchdog Timer interrupt is taken.
Table 13-27. Watchdog Timer Interrupt—Register Settings
Register
Setting Description
CSRR0
CSRR1
MSR
ESR
MCSR
Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
Set to the contents of the MSR at the time of the interrupt
UCLE 0
SPE 0
WE 0
CE 0
EE 0
PR 0
FP 0
ME —
FE0 0
DE 0/—¹
FE1 0
IS 0
DS 0
PMM 0
RI —
Unchanged
Unchanged
13-36
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor