PXR40RM Datasheet, PDF (1051/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
When the EQADC_CFPRx is written and CFIFOx is not full, the CFIFO counter CFCTRx is incremented
by one, and the Push Next Data Pointer x then is incremented by one (or wrapped around) to point to the
next entry in the CFIFO.
When the EQADC_CFPRx is written but CFIFOx is full, the EQADC will not increment the counter value
and will not overwrite any entry in CFIFOx.
Write to slave-bus
interface by CPU or
DMA
CFIFO
Push Register
Push Next
Data Pointer *
--------------------
--------------------
32-bit Entry 2
32-bit Entry 1
Transfer Next
Data Pointer *
DMA Done
Interrupt/DMA Request
Control
Signals
CFIFO
Transfer Counter
Control Logic
* All CFIFO entries are memory mapped and the
entries addressed by these pointers can have their
absolute addresses calculated using TNXTPTR
and CFCTR.
Figure 27-49. CFIFO Diagram
The detailed behavior of the Push Next Data Pointer and Transfer Next Data Pointer is described in the
example shown in Figure 27-50 where a CFIFO with 16 entries is shown for clarity of explanation, the
actual hardware implementation has only four entries. In this example, CFIFOx with 16 entries is shown
in sequence after pushing and transferring entries.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-69