PXR40RM Datasheet, PDF (1317/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Chapter 31
Nexus Development Interface (NDI)
Nexus Development Interface (NDI)
31.1 Introduction
The device microcontroller contains multiple Nexus clients that communicate over a single IEEE-ISTO
5001™-2003 Nexus class 3 combined JTAG IEEE 1149.1/auxiliary out interface. Combined, all of the
Nexus clients are referred to as the Nexus development interface (NDI). Class 3 Nexus allows for program,
data, and ownership trace of the microcontroller execution without access to the external data and address
buses.
This chapter is organized into sections that provide a high level view of the Nexus development interface:
Section 31.1, Introduction, through Section 31.8, NPC Initialization and Application Information.
The chapter contains sections that discuss the modules of the Nexus development interface:
• Nexus dual-eTPU development interface (NDEDI). The device has two eTPU engines. See
Section 31.9, Nexus Dual eTPU Development Interface (NDEDI), and the eTPU Reference
Manual for information about the NDEDI.
• Nexus e200z7 core interface (NZ7C3). In this chapter, the NZ7C3 interface is discussed in
Section 31.10, e200z7 Class 3 Nexus Module (NZ7C3) through Section 31.11, NZ7C3 Memory
Map and Register Definition.
• Nexus crossbar eDMA interface (NXDM) and Nexus FlexRay interface (NXFR). Refer to
Section 31.15, Nexus Crossbar eDMA Interface (NXDM) and Nexus Crossbar FlexRay Interface
(NXFR).
Communication to the NDI is managed via the auxiliary port and the JTAG port.
• The auxiliary port is comprised of 17 or 21 output pins and 1 input pin. The output pins include
one message clock out (MCKO) pin, 12 or 16 message data out (MDO) pins, two message start/end
out (MSEO) pins, one ready (RDY) pin, and one event out (EVTO) pin. Event in (EVTI) is the only
input pin for the auxiliary port.
• The JTAG port consists of four inputs and one output. These pins include JTAG compliance select
(JCOMP), test data input (TDI), test data output (TDO), test mode select (TMS), and test clock
input (TCK). TDI, TDO, TMS, and TCK are compliant with the IEEE 1149.1-2001 standard and
are shared with the NDI through the test access port (TAP) interface. JCOMP along with power-on
reset and the TAP state machine are used to control reset for the NDI module. Ownership of the
TAP is achieved by loading the appropriate enable instruction for the desired Nexus client in the
JTAG controller (JTAGC) when JCOMP is asserted. See Table 31-4 for the JTAGC opcodes to
access the different Nexus clients.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
31-1