PXR40RM Datasheet, PDF (1049/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
NOTES:
1 _{VREF=VRH-VRL=5.12V. Resulting in one 12-bit count (LSB) =1.25mV.}
2 _{The two’s complement representation is used to express negative values.}
3
For non-corner voltages (voltages different from V_RL and V_RH), the maximum quantization error is 0.5 LSB. First
code transition (from 0x000 to 0x001 for unsigned values) happens at +0.5 LSB (V) while the last one (from 0xFFE
to 0xFFF for unsigned values) happens at V_REF - 1.5 LSB (V).
4
For non-corner voltages (voltages different from V_RL and V_RH), the maximum quantization error is 0.5 LSB. First
code transition (from 0x000 to 0x001 for unsigned values) happens at +0.5 LSB (V) while the last one (from 0xFFE
to 0xFFF for unsigned values) happens at V_REF - 1.5 LSB (V).
5
For non-corner voltages (voltages different from V_RL and V_RH), the maximum quantization error is 0.5 LSB. First
code transition (from 0x000 to 0x001 for unsigned values) happens at +0.5 LSB (V) while the last one (from 0xFFE
to 0xFFF for unsigned values) happens at V_REF - 1.5 LSB (V).
6 _{Assuming uncalibrated conversion results.}
27.7.3 Command/Result Queues
Each CQueue entry is a 32-bit Command Message.The last entry of a CQueue has the EOQ bit asserted to
indicate that it is the last entry of the CQueue. RQueue entry is a 16-bit data.
See Section 27.7.2.1, Overview and Basic Terminology, for a description of the message formats and their
flow in EQADC.
Refer to Section 27.8.5, CQueue and RQueues Usage, for examples of how CQueues and RQueues can be
used.
27.7.4 EQADC Command FIFOs
27.7.4.1 CFIFO Basic Functionality
There are six prioritized CFIFOs located in the EQADC. Each CFIFO is four entries deep, except CFIFO0
that can be configured to eight entries deep in extended mode, and each CFIFO entry is 32 bits long. A
CFIFO serves as a temporary storage location for the command messages stored in the CQueues in the
system memory. When a CFIFO is not full, the EQADC sets the corresponding CFFF bit in
EQADC_FISR. If CFFE is asserted in EQADC_IDCR, the EQADC generates requests for more
commands from a CQueue. An interrupt request, served by the host CPU, is generated when CFFS is
negated, and a DMA request, served by the DMAC, is generated when CFFS is asserted. The host CPU or
the DMAC respond to these requests by writing to the EQADC_CFPR to fill the CFIFO.
NOTE
The DMAC should be configured to write a single command (32-bit data)
to the CFIFO push registers for every asserted DMA request it
acknowledges. Refer to Section 27.8.2, EQADC/DMAC Interface, for
DMAC configuration guidelines.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-67