PXR40RM Datasheet, PDF (38/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Table ii. Notational Conventions (continued)
Instruction
Operand Syntax
An
Ay,Ax
Dn
Dy,Dx
Rc
Rm
Rn
Rw
Ry,Rx
Xi
#<data>
<ea>
<ea>y,<ea>x
<label>
<list>
<shift>
<size>
bc
dc
ic
# <vector>
<>
<xxx>
dn
SF
+
–
x
Register Specifications
Any address register n (example: A3 is address register 3)
Source and destination address registers, respectively
Any data register n (example: D5 is data register 5)
Source and destination data registers, respectively
Any control register (example VBR is the vector base register)
MAC registers (ACC, MAC, MASK)
Any address or data register
Destination register w (used for MAC instructions only)
Any source and destination registers, respectively
Index register i (can be an address or data register: Ai, Di)
Miscellaneous Operands
Immediate data following the 16-bit operation word of the instruction
Effective address
Source and destination effective addresses, respectively
Assembly language program label
List of registers for MOVEM instruction (example: D3–D0)
Shift operation: shift left (<<), shift right (>>)
Operand data size: byte (B), word (W), longword (L)
Instruction and data caches
Data cache
Instruction cache
Identifies the 4-bit vector number for trap instructions
identifies an indirect data address referencing memory
identifies an absolute address referencing memory
Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Operations
Arithmetic addition or postincrement indicator
Arithmetic subtraction or predecrement indicator
Arithmetic multiplication
xxxviii
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor